1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, in particular, characterized by a stack structure of insulating layers which permits formation of minute via-holes without defects through a low-temperature process in a semiconductor highly-integrated circuit device such as a hybrid system LSI including a DRAM (Dynamic Random Access Memory).
2. Description of the Related Art
In recent progress of integration of semiconductor integrated circuit devices, SAC (Self-Align Contact) method, MDC (Modified Contact) method, PSC (Poly Shrink Contact) method, etc., are known for forming a minute via-hole in the manner that an opening portion is formed in an insulating layer interposed between interconnection layers. These methods of forming via-holes will be described below with reference to FIGS. 1A through 1C to FIGS. 4A through 4C.
First, a conventional SAC process will be described with reference to FIGS. 1A through 1C.
Referring first to FIG. 1A, interconnection lines 52 for, e.g., bit lines, are formed on an insulating underlayer 51 made of, e.g., SiO2, according to a design rule of 0.16 μm/0.24 μm for line/space. A SiN film is then formed by deposition, and anisotropically etched to form spacers 54.
In this case, for surely forming a certain space between the interconnection lines 52, the thickness of the SiN film must be 0.12 μm or less.
Note that, on the upper surface of each interconnection line 52, another SiN film 53 has been formed prior to the formation of the above-described SiN film. Besides, an electrode plug (not shown) has been provided at the portion in the insulating underlayer 51 corresponding to the space between the interconnection lines 52.
A thick insulating interlayer 55 made of, e.g., BPSG, is then formed on the entire surface by deposition. The surface of the insulating interlayer 55 is flattened through a CMP (Chemical Mechanical Polishing) or etch-back process. A resist pattern (not shown) for 0.24 μm-wide via-holes is formed using a photolithographic technique. Anisotropic etching is carried out using the SiN films 53 and the spacers 54 as etching stoppers, to form a via-hole 56.
Referring next to FIG. 1B, a thick amorphous Si layer 57 doped with, e.g., P (phosphorus), is formed on the entire surface by deposition.
Referring next to FIG. 1C, polishing by CMP method is carried out until the surface of the insulating interlayer 55 is exposed. The part of the doped amorphous Si layer 57 formed on the insulating interlayer 55 is thereby removed to form a Si plug 58 filling in the via-hole 56.
Next, a conventional MDC process will be described with reference to FIGS. 2A through 2D.
Referring first to FIG. 2A, interconnection lines 52 for, e.g., bit lines, are formed on an insulating underlayer 51 made of, e.g., SiO2, according to a design rule of 0.16 μm/0.24 μm for line/space. A thick insulating interlayer 55 made of, e.g., BPSG, is then formed on the entire surface by deposition. The surface of the insulating interlayer 55 is flattened through a CMP or etch-back process. A resist pattern (not shown) for 0.24 μm-wide via-holes is formed using a photolithographic technique. Anisotropic etching is carried out using the interconnection lines 52 as etching stoppers, to form a via-hole 56.
An electrode plug (not shown) has been provided at the portion in the insulating underlayer 51 corresponding to the space between the interconnection lines 52.
Referring next to FIG. 2B, an insulating film 59 made of, e.g., SiN, having an etching selectivity to the BPSG film, is formed by deposition.
In this case, for surely forming a certain space between the interconnection lines 52 in the subsequent anisotropic etching process, the thickness of the insulating film 59 must be 0.12 μm or less, in particular, 0.1 μm or less.
Referring next to FIG. 2C, anisotropic etching is carried out to form spacers 60, which newly define a via-hole 61 between them.
Referring next to FIG. 2D, a thick amorphous Si layer doped with, e.g., P (phosphorus), is formed on the entire surface by deposition. Polishing by CMP method is then carried out until the surface of the insulating interlayer 55 is exposed. The part of the doped amorphous Si layer formed on the insulating interlayer 55 is thereby removed to form a Si plug 62 filling in the via-hole 61.
Next, a conventional PSC process will be described with reference to FIGS. 3A through 3C and 4A through 4C.
Referring first to FIG. 3A, interconnection lines 52 for, e.g., bit lines, are formed on an insulating underlayer 51 made of, e.g., SiO2, according to a design rule of 0.16 μm/0.24 μm for line/space. A thick insulating interlayer 55 made of, e.g., BPSG, is then formed on the entire surface by deposition. The surface of the insulating interlayer 55 is flattened through a CMP or etch-back process. An amorphous Si layer 63 having an etching selectivity to the insulating interlayer 55 is then formed on the entire surface by deposition, into a thickness of, e.g., 0.3 μm.
An electrode plug (not shown) has been provided at the portion in the insulating underlayer 51 corresponding to the space between the interconnection lines 52.
Referring next to FIG. 3B, a resist pattern (not shown) for 0.24 μm-wide via-holes is formed using a photolithographic technique. Anisotropic etching is then carried out using the insulating interlayer 55 as an etching stopper, to form an opening portion 64 in the amorphous Si layer 63.
Referring next to FIG. 3C, another amorphous Si layer is formed on the entire surface by deposition, into a thickness of, e.g., 0.12 μm or less. Anisotropic etching is then carried out to form Si spacers 65, which newly define an opening portion 66 between them.
Referring next to FIG. 4A, anisotropic etching is carried out using the amorphous Si layer 63 and the Si spacers 65 as etching masks, to form a via-hole 67.
Referring next to FIG. 4B, a thick amorphous Si layer 68 doped with, e.g., P (phosphorus), is formed on the entire surface by deposition.
Referring next to FIG. 4C, polishing by CMP method is carried out until the surface of the insulating interlayer 55 is exposed. The part of the doped amorphous Si layer 68 formed on the insulating interlayer 55 is thereby removed to form a Si plug 69 filling in the via-hole 67.
Next, a manufacturing method of a conventional hybrid system LSI including a DRAM will be described with reference to FIGS. 5A and 5B to FIGS. 14A and 14B, in which a via-hole for a storage node is formed through a PSC process among techniques for forming such a via-hole in a self aligning manner.
FIGS. 5A, 7A, 9A, 11A and 13A are sectional views of a memory cell portion. FIGS. 5B, 7B, 9B, 11B and 13B are sectional views of an alignment mark portion at the same stages as those of FIGS. 5A, 7A, 9A, 11A and 13A, respectively. FIGS. 6A, 8A, 10A, 12A and 14A are sectional views perpendicular to those of FIGS. 5A, 7A, 9A, 11A and 13A, respectively. FIGS. 6B, 8B, 10B, 12B and 14B are sectional views of a logic transistor portion.
Referring first to FIGS. 5A to 6B, electrically insulating regions 72 for element isolation are formed in a p-type silicon substrate 71 through an STI (Shallow Trench Isolation) process.
The p-type silicon substrate 71 may be substituted by a p-type well formed in an n- or p-type silicon substrate. Besides, channel stop regions or doped channel regions may be formed therein through an ion implantation process, at need.
Next, a gate oxide film 73 is formed by thermal oxidation using wet O2 gas. An amorphous Si film is then formed by deposition into a thickness of, e.g., 100 nm. The amorphous Si film is doped with As or P by ion implantation. A conductive Si gate electrode layer 74 is obtained thereby.
Next, a 100 nm-thick WSi2 film 75 is formed by deposition, for example. Subsequently, a 100 nm-thick P—SiN film 76 is formed through a plasma CVD process, for example. After this, in the DRAM portion, patterning by etching are carried out using a photolithographic technique, according to a design rule of, e.g., 0.20 μm/0.20 μm for line/space, to form gate electrodes and word lines successive from the gate electrodes.
The length of the gate electrode in the logic transistor portion of FIG. 6B is, e.g., 0.18 μm.
Next, for n-channel FET portions, ion implantation with P is carried out. In the DRAM portion, n-type drain and source regions 77 and 78 are formed thereby. At the same time, in the logic transistor portion, n-type LDD (Lightly Doped Drain) regions 79 are formed.
Next, a SiN film 80 of a thickness of, e.g., 60 nm, is formed on the entire surface through a CVD process. After this, while masking the DRAM portion with a resist, anisotropic etching is carried out to form a spacer 81 on either side wall of the gate electrode in the logic transistor portion. Ion implantation with As is then carried out using the spacers 81 as masks, to form n+-type drain and source regions 82 and 83. After this, defects attendant upon ion implantation are repaired through an RTA (Rapid Thermal Anneal) process, e.g., heat treatment at 1000° C. for 10 seconds.
Next, a Co film is formed on the entire surface by deposition, into a thickness of, e.g., 50 nm. Heat treatment at 500° C. for 30 seconds is then carried out to form silicide electrodes 84 of CoSi2 only on the surfaces of the n+-type drain and source regions 82 and 83. Subsequently, etching is carried out with a mixture solution of hydrogen peroxide and ammonia or a mixture solution of sulfuric acid and hydrogen peroxide to remove unreacted Co.
Next, a SiN film 85 of a thickness of, e.g., 20 nm, is formed on the entire surface through a CVD process.
In this case, by forming the SiN film 85 in a growth device with a load lock system, oxidation of the silicide electrodes 84 by oxygen engulfed during the growth of the SiN film 85 can be successfully prevented.
Next, a BPSG film 86 is formed on the entire surface by deposition. In the DRAM portion, bit and storage contacts are then formed through an SAC process.
In this case, after a resist pattern (not shown) for 0.24 μm-wide via-holes is formed using a photolithographic technique, the BPSG film 86 is etched by double-channel RIE (Reactive Ion Etching) using C4F8+CO+Ar+O2 gas. Subsequently, the SiN film 85 is etched to expose the n-type drain and source regions 77 and 78.
In this etching process, sidewalls 87 are formed on the opposed side surfaces of the gate electrodes. These sidewalls 87 prevent short circuits between the gate electrodes and Si plugs 88 and 89 which will be described later.
As the capacitance on each gate electrode, i.e., word line, the capacitance between it and the p-type silicon substrate 71 across the gate oxide film 73 is dominant. Therefore, an increase in capacitance due to use of SAC method matters little.
Next, a thick amorphous Si layer doped with, e.g., P, is formed by deposition. Polishing is then carried out until the surface of the BPSG film 86 is exposed. The part of the doped amorphous Si layer formed on the BPSG film 86 is thereby removed to form Si plugs 88 and 89 filling in via-holes.
Next, a P—SiO2 film 90 of a thickness of, e.g., 100 nm, is formed on the entire surface through a plasma CVD process. A via-hole is then formed for the Si plug 88 which is to serve as a bit contact. After this, a Ti film of a thickness of, e.g., 20 nm, a TiN film of a thickness of, e.g., 50 nm, and a W film of a thickness of, e.g., 100 nm, are formed in order on the entire surface by deposition. These films are then patterned into a predetermined shape to form bit lines 91 of the Ti/TiN/W structure.
In this case, the bit lines 91 are formed according to a design rule of 0.16 μm/0.24 μm for line/space, for example.
At this time, in the alignment mark portion, alignment marks 92 of the Ti/TiN/W structure are formed, as shown in FIG. 5B.
Next, a SiO2 film 93 of a thickness of, e.g., 700 nm, is formed through an HDP (High Density Plasma)-CVD process. Subsequently, the SiO2 film 93 is polished by about 200 nm through a CMP process to flatten the surface of the SiO2 film 93.
Referring next to FIGS. 7A to 8B, an amorphous Si layer 94 of a thickness of, e.g., 300 nm, is formed on the entire surface by deposition. The part of the amorphous Si layer 94 above the alignment marks 92 is then removed by rough patterning to form a window portion 95.
This is because the amorphous Si layer 94 is opaque in relation to visible light. That is, when such a thick amorphous Si layer 94 having its thickness of 300 nm is present above the alignment marks 92, detection of the alignment marks 92 may become impossible.
Referring next to FIGS. 9A to 10B, a resist pattern (not shown) for via-holes of a width of 0.24 μm(=240 nm) is formed using a photolithographic technique. Subsequently, anisotropic etching is carried out to form an opening portion at the position in the amorphous Si layer 94 corresponding to the Si plug 89 which is to serve as a storage contact. After this, another amorphous silicon layer of a thickness of, e.g., 95 nm, is formed on the entire surface by deposition. Subsequently, anisotropic etching is carried out to form Si spacers 95 whose maximum width is 95 nm. After this, anisotropic etching is carried out using the Si spacers 95 and the amorphous Si layer 94 as masks, to form a via-hole 98 whose minimum width is 0.05 μm(=50 nm=240 nm−2×95 nm).
At this time, the alignment mark portion is covered with a resist 97, thereby preventing the SiO2 film 93 at that portion from being etched off to expose the alignment marks 92.
Referring next to FIGS. 11A to 12B, an amorphous Si layer of a thickness of, e.g., 200 nm, doped with, e.g., P, is formed on the entire surface by deposition. Subsequently, polishing is carried out until the surface of the SiO2 film 93 is exposed through a CMP process. The part of the doped amorphous Si layer formed on the amorphous Si layer 94, the amorphous Si layer 94, and the Si spacers 95 are thereby removed to form a Si plug 99 filling in the via-hole 98.
At this time, a lower part of each Si spacer 95 may remain as a residual Si spacer portion 100.
Referring next to FIGS. 13A to 14B, an LP—SiN film 101 which is to serve as etching stoppers in the subsequent stages, is formed into a thickness of, e.g., 10 nm, through a low-pressure chemical vapor deposition (LPCVD) process. A BPSG film (not shown) of a thickness of, e.g., 1 μm, is then formed on the entire surface by deposition.
Next, the BPSG film and the LP—SiN film 101 are etched in order, to form a wide opening portion which reaches the Si plug 99 formed by PSC method. After this, an amorphous Si layer of a thickness of, e.g., 50 nm, doped with P, is formed on the entire surface by deposition. Subsequently, the part of the doped amorphous Si layer formed on the BPSG film is removed through a CMP process to form a storage node 102 having cylindrical outer and inner surfaces.
Next, the BPSG film is selectively removed with an HF aqueous solution using the LP—SiN film 101 as an etching stopper. Subsequently, a SiN film of a thickness of, e.g., 5 nm, is formed on the surface of the storage node 102 through an LPCVD process at, e.g., 700° C. The SiN film is to serve as a dielectric layer of a capacitor. After this, an amorphous Si film of a thickness of, e.g., 100 nm, doped with P, is formed on the entire surface by deposition to form a cell plate 103 common for storage nodes 102.
In the subsequent process not illustrated, an insulating interlayer is formed on the entire surface. Heat treatment by RTA method at 900° C. for 10 seconds is carried out for re-activation to ensure a certain current of each MOSFET. After this, wiring process and so on are performed. A system LSI in which a DRAM is incorporated is obtained thereby.
In the above RTA process for re-activation, since no thick plasma SiN film exists, peeling or cracking thereof never occurs.
The above-described conventional formation methods of via-holes, however, include various problems. This will be discussed below.
For example, in case of the SAC method as shown in FIGS. 1A to 1C, the device has a COB (Capacitor Over Bit-line) structure in which interconnection lines 52, i.e., bit lines, are under the capacitor. When the via-hole 56 is for a storage node contact, if the via-hole 56 is formed through a usual selective etching process with double-channel RIE using C4F8+CO+Ar+O2 gas, the side surface of each interconnection line 52 must be covered with a SiN film having an etching selectivity in relation to the insulating interlayer 55 made of, e.g., BPSG.
However, such a SiN film has a high relative dielectric constant. Besides, in case of SAC method, the area of the opening of the via-hole 56 over the interconnection lines 52 cannot but be large in comparison with that of MDC or PSC method. This causes the problem that the capacitance between each bit line and the storage node increases.
For example, when the relative dielectric constant of SiN is represented by ε, the dielectric constant of vacuum is represented by ε0, the surface area is represented by S, and the distance between the electrodes is represented by d, the capacity C of the capacitor is expressed by:C=(ε×ε0×S/d)
The relative dielectric constant of SiN is 7.4, which is approximately double that of SiO2.
Such an increase in capacity makes it hard to reduce the number of sense amplifier divisions. This causes an increase in chip area.
Next, problems in use of the MDC method as shown in FIGS. 2A to 2D will be discussed. When each spacer 60 in the via-hole 56 is made of SiN, there arises the problem of increasing the capacity between each bit line and the storage node, like the case of the above-discussed SAC method.
Otherwise, it is thinkable that each spacer 60 in the via-hole 56 is made of SiO2 whose relative dielectric constant is low. In this case, however, the following problems arise. The film for forming such a spacer is required to have a good step coverage ability. On the other hand, as a demand of such a hybrid system LSI including a DRAM, in order to prevent deterioration of performance of a logic circuit because of, e.g., occurrence of short-channel effect due to change in impurity profile of source/drain regions, a low-temperature process is required for the DRAM having a COB structure. For example, a furnace annealing process at 700° C. or less is required.
As a method for forming a SiO2 film with good step coverage ability through such a low-temperature process, known is LP-TEOS method capable of forming a film at 650° C. However, the LP-TEOS film formed by this method can not be densified and reduces in its anti-breakdown property unless it is subjected to a heat treatment at about 800° C. in the atmosphere of N2. Therefore, this method can not be used for such a hybrid system LSI including a DRAM.
No other formation method of a SiO2 film with good step coverage ability through a low-temperature process is present if mass-productivity in a factory is taken into consideration.
Next, problems in use of the PSC method as shown in FIGS. 3A to 3C and FIGS. 4A to 4C will be discussed. If a hard mask and spacers formed on the side surfaces thereof, which are to serve as etching masks, are made of polycrystalline Si, since polycrystalline Si is opaque in relation to visible light, alignment marks cannot be detected upon formation of via-holes, as described in connection with FIG. 7B.
With recent progress of minuteness in semiconductor device, resolution in photolithographic process has also been improved. Since the higher resolution requires the shallower focal depth, the surface of the insulating interlayer 55 must be flattened. If the surface has been flattened, however, unevenness in height caused by the alignment marks for photolithography may disappear, and detection of the alignment marks may become impossible through the opaque film.
For this reason, as described in connection with FIG. 7B, for removing the amorphous Si layer 93 over the alignment marks 92, two steps of resist pattern formation and etching are necessary as extra steps. Furthermore, in order to prevent the alignment marks 92 from being exposed during the formation process of the via-hole 98, a formation process of the resist 97 is necessary. These hinder a reduction of cost and a higher throughput.
Besides, in case of bit lines 91 made of a metal, if the alignment marks 92 are formed at a level of an interconnection layer lower than the bit lines 91, the alignment must be done indirectly and so the positional deviation may become large. For this reason, the alignment marks are usually formed using the bit lines 91. In this case, however, if the formation process of the resist 97 is omitted, the metal alignment marks 92 may be exposed during the formation process of the via-hole 98. This may cause a metallic contamination of the depositing device for the doped amorphous Si layer for forming the Si plug in the subsequent stage. Therefore, the device only for that process must be used. In a usual factory, however, such a limited use of the device is hard.
Consequently, when the bit lines are made of a metal, the three extra steps in total become necessary.
Further, problems in a minute via-hole formation process by the PSC method in which furnace annealing only at 700° C. or less can be carried out because metal interconnection lines exist in a lower layer as represented by a hybrid system LSI including a DRAM, will be discussed with reference to FIG. 15.
Referring to FIG. 15, when a via-hole 67 is formed in a 500 nm-thick insulating interlayer 55, an amorphous Si layer 63 as a hard mask requires its thickness of 300 nm.
This is because the plasma in the etching process for forming the via-hole 67 is apt to concentrate at corner portions, and so etching rapidly progresses in the interface between the amorphous Si layer 63 and each Si spacer 65. This may result in generation of abnormal etching portions 70.
Alternatively, when an LP—SiN film formed through an LPCVD process is used as the hard mask, 270 minutes(=4.5 hours) is required for the LP—SiN film having grown to a thickness of 300 nm at 700° C. or less. This causes a problem on throughput.
Besides, when a plasma CVD process is used for the hard mask and a BPSG film exists in the lower layer, the P—SiN film formed through the process may crack if its thickness is 100 nm or more.
More specifically, When the P—SiN film is put in a formation process of a capacitor dielectric film or a RTA process for re-activation of source/drain regions after formation of the via-hole 67, the stress exerted on the P—SiN film changes from compression to tensile due to heat of 650° C. or more. This may cause peeling off or cracking.